1. Field of the Invention
The present invention relates to a microcomputer having a register file formed by a built-in RAM, and more particularly, to a data transfer system between registers for the microcomputer which can speed up data transfer between registers in the register file.
2. Description of the Prior Art
FIG. 5 is a block diagram of the configuration of a microcomputer having a register file formed by a conventional built-in RAM. In the figure, reference numeral 1 represents the register file formed by the built-in RAM, 2 an internal data bus, 3 and 4 temporary registers, 5 an arithmetic logic unit (abbreviated as ALU hereinafter) for performing various operations on data inputted from the internal data bus 2 through the temporary registers 3 and 4 and outputting the results of operations to the internal data bus 2, and 6 a data pointer for holding an address for specifying a register in the register file.
The operation of the conventional microcomputer shown in FIG. 5 when instructions to perform the processing of data transfer between registers in the register file 1 and the processing of incrementing the data pointer are executed will be explained hereafter. The contents of the instructions to be executed are to transfer data stored in the register Rm in the register file 1 to a register (Rn for example) specified by the data pointer 6 and to increment the data pointer by one. The mnemonic of the instructions is MOV Rm, @+1. To execute the instructions MOV Rm, @+1, two operations by the ALU 5 are required. The first operation is for the transfer of data stored in the register Rm to the register Rn, and the second operation for incrementing the data pointer 6.
FIG. 6 and FIG. 7 are diagrams illustrating data flows for these two operations by the ALU 5, and constituent circuits are the same as those shown in FIG. 5. For the first operation, data stored in the register Rm of the register file 1 is first read and stored in the temporary register 3 through the internal data bus 2 (dotted line a of FIG. 6). Thereafter, a constant data "0" is set in the temporary register 4 by an unshown control section, and the ALU 5 is controlled by this unshown control section so that the logical sum (OR) of both data in the temporary registers 3 and 4 is calculated by the ALU 5. Finally, data outputted from the ALU 5 is transferred to the register file 1 through the internal data bus 2 and written in the register Rn (dotted line b of FIG. 6).
Then, for the second operation of the ALU 5, the processing of incrementing the data pointer 6 by one is performed. First, the contents of the data pointer 6 are stored in the temporary register 3 through the internal bus 2 (dotted line c of FIG. 7). Thereafter, a constant data "1" is set in the temporary register 4 by the unshown control section, and the ALU 5 is controlled by the unshown control section, whereby the addition of both data in the temporary registers 3 and 4 is performed. Finally, data outputted from the ALU 5 is written back in the data pointer 6 through the internal data bus 2 as the result of addition (dotted line d of FIG. 7).
FIG. 8 shows the processing steps of data transfer between registers in the conventional microcomputer described above which are arranged in sequence of time. An instruction to transfer data was decoded by an unshown instruction decoding section (step S10), data transfer between registers was carried out (step S11), the processing of controlling the data pointer was performed (step S12), and the next instruction was decoded by the unshown instruction decoding section.
In the conventional microcomputer as described above, in case of data transfer between registers in the register file, the processing of controlling the data pointer (step S12) was performed after data transfer between registers (step S11). In other words, in case of data transfer from a source register to a desired destination register, data read from the source register was written in the destination register through the operation of the ALU. Because of this, data transfer speed between the registers is slow. In addition, hardware resources such as the ALU and the temporary registers could not be used during data transfer because the ALU, the temporary registers and the internal bus were used for this simple transfer operation unaccompanied by data processing such as addition and subtraction.